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ICS9LPRS480 bảng dữ liệu(PDF) 19 Page - Integrated Device Technology |
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ICS9LPRS480 bảng dữ liệu(HTML) 19 Page - Integrated Device Technology |
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19 / 25 page  19 Integrated Circuit Systems, Inc. ICS9LPRS480 1391D—02/02/09 SMBus Table: Byte Count Register Byte 8 Name Control Function Type 0 1 Default Bit 7 0 Bit 6 0 Bit 5 BC5 Byte Count bit 5 (MSB) RW 0 Bit 4 BC4 Byte Count bit 4 RW 0 Bit 3 BC3 Byte Count bit 3 RW 1 Bit 2 BC2 Byte Count bit 2 RW 1 Bit 1 BC1 Byte Count bit 1 RW 1 Bit 0 BC0 Byte Count bit 0 (LSB) RW 1 SMBus Table: WatchDog Timer Control Register Byte 9 Name Control Function Type 0 1 Default Bit 7 HWD_EN Watchdog Hard Alarm Enable RW Disable and Reload Hartd Alarm Timer, Clear WD Hard status bit. Enable Timer 0 Bit 6 SWD_EN Watchdog Soft Alarm Enable RW Disable Enable 0 Bit 5 WD Hard Status WD Hard Alarm Status R Normal Alarm X Bit 4 WD Soft Status WD Soft Alarm Status R Normal Alarm X Bit 3 WDTCtrl Watch Dog Alarm Time base Control RW 290ms Base 1160ms Base 0 Bit 2 HWD2 WD Hard Alarm Timer Bit 2 RW 1 Bit 1 HWD1 WD Hard Alarm Timer Bit 1 RW 1 Bit 0 HWD0 WD Hard Alarm Timer Bit 0 RW 1 SMBus Table: WD Timer Safe Frequency Control Register Byte 10 Name Control Function Type 0 1 Default Bit 7 SWD2 WD Soft Alarm Timer Bit 2 RW 1 Bit 6 SWD1 WD Soft Alarm Timer Bit 1 RW 1 Bit 5 SWD0 WD Soft Alarm Timer Bit 0 RW 1 Bit 4 WD SF4 RW 0 Bit 3 WD SF3 RW 0 Bit 2 WD SF2 RW 1 Bit 1 WD SF1 RW 1 Bit 0 WD SF0 RW 1 SMBus Table: CPU PLL Frequency Control Register Byte 11 Name Control Function Type 0 1 Default Bit 7 N Div2 N Divider Prog bit 2 RW X Bit 6 N Div1 N Divider Prog bit 1 RW X Bit 5 M Div5 RW X Bit 4 M Div4 RW X Bit 3 M Div3 RW X Bit 2 M Div2 RW X Bit 1 M Div1 RW X Bit 0 M Div0 RW X These bits represent the number of Watch Dog Time Base Units that pass before the Watch Alarm expires. Default is 7 X 290ms = 2s. Watch Dog Safe Freq Programming bits The decimal representation of M and N Divider in Byte 11 and 12 will configure the VCO frequency. Default at power up = Byte 3 Rom table. VCO Frequency = 14.318 x Ndiv(10:0)/Mdiv(5:0) . M Divider Programming bits These bits represent the number of Watch Dog Time Base Units that pass before the Watch Alarm expires. Default is 7 X 290ms = 2s. Determines the number of bytes that are read back from the device. Default is 0F hex. These bits configure the safe frequency that the device returns to if the Watchdog Timer expires. The value show here corresponds to the power up default of the device. See the various Frequency Select Tables for the exact frequencies. Reserved Reserved |
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