LIS3DHTR datasheet(18/42 Pages) STMICROELECTRONICS

18 / 42 page

Application hints

LIS3DH

18/42

Doc ID 17530 Rev 1

Application hints

Figure 5.

LIS3DH electrical connection

The device core is supplied through Vdd line while the I/O pads are supplied through

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 µF aluminum) should

be placed as near as possible to the pin 14 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper

behavior of the IC (refer to Figure 5). It is possible to remove Vdd maintaining Vdd_IO

without blocking the communication bus, in this condition the measurement chain is

powered off.

The functionality of the device and the measured acceleration data is selectable and

accessible through the I2C or SPI interfaces.When using the I2C, CS must be tied high.

The ADC1, ADC2 & ADC3 if not used can be left floating or keep connected to Vdd or GND.

The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be

completely programmed by the user through the I2C/SPI interface.

4.1

Soldering information

The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com.

10µF

Vdd

100nF

GND

Vdd_IO

INT1

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

TOP VIEW

INT2

ADC2

ADC1

ADC3

Vdd_IO

Rpu

Pull-up to be added

when I2C interface is used

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