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SM5M2 bảng dữ liệu(PDF) 22 Page - Sharp Corporation |
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SM5M2 bảng dữ liệu(HTML) 22 Page - Sharp Corporation |
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22 / 28 page ![]() SM5M2 - 22 - Hardware Reset Function The hardware reset function mode activated two instruction cycles after the falling edge from the RESET pin. When the RESET pin is changed from High to Low, the pulse which is input by the OSCIN pin is counted 215 times after which the reset mode clears and the program counter starts from address 0 on page 0. The initialized status of the system after reset is shown in Table 7. The following reset functions are available. • The I/O port is set as an input port and the mode register RC, RD, RE and RF are cleared. The output only port (P0) is cleared and output Low. • The interrupt request flags (IFA, IFD) and the interrupt enable flag (IME) are cleared and all interrupts become disabled. • The program counter start from step 0 on page 0. For activate reset function, when power is turned on, you must connect a capacitor (0.1 µF, TYP.) across the RESET pin and GND. Table 7 Reset Status NOTES : • Undefined flags and registers should be initialized by software. • When all of P1 pins (P10 to P13) level goes to High, the SM5M2 is performed to reset operation. (Mask option) FLAG OR REGISTER, X-REGISTER STATUS ( in reset mode and at program start) PC 0 SP Level 1 RAM Undefined ACC Undefined X-register Undefined P0-P2 output latch registers 0 Divider 0 IFA flag 0 IFD flag 0 IME flag 0 0 C flag P33 flag Undefined BM, BL registers Undefined Register RC (bit 7-0) Register RD (bit 1) Register RD (bit 0) 0 Undefined Register RE (bit 2, 1, 0) 0 Register RF (bit 3, 2, 1, 0) Register RD (bit 3) Register RD (bit 2) 0 0 0 0 |
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