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MXB7843EEE bảng dữ liệu(PDF) 13 Page - Maxim Integrated Products |
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MXB7843EEE bảng dữ liệu(HTML) 13 Page - Maxim Integrated Products |
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13 / 21 page ![]() Digital Interface Initialization After Power-Up and Starting a Conversion The digital interface consists of three inputs, DIN, DCLK, CS, and one output, DOUT. A logic-high on CS disables the MXB7843 digital interface and places DOUT in a high-impedance state. Pulling CS low enables the MXB7843 digital interface. Start a conversion by clocking a control byte into DIN (Table 3) with CS low. Each rising edge on DCLK clocks a bit from DIN into the MXB7843’s internal shift register. After CS falls, the first arriving logic 1 bit defines the control byte’s START bit. Until the START bit arrives, any number of logic 0 bits can be clocked into DIN with no effect. The MXB7843 is compatible with SPI/QSPI/MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers of the micro- controller: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. The simplest software interface requires only three 8-bit transfers to perform a conversion (one 8- bit transfer to configure the ADC, and two more 8-bit transfers to read the conversion result) (Figure 7). Simple Software Interface Make sure the CPU’s serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 500kHz to 2MHz: 1) Set up the control byte and call it TB. TB should be in the format: 1XXXXXXX binary, where X denotes the particular channel, selected conversion mode, and power mode (Tables 3, 4). 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB and simultaneously receive a byte; call it RB1. 4) Transmit a byte of all zeros ($00 hex) and simultane- ously receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and simultane- ously receive byte RB3. 6) Pull CS high. Figure 7 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion, padded by four trailing zeros. The total conversion time is a func- tion of the serial-clock frequency and the amount of idle timing between 8-bit transfers. Digital Output The MXB7843 outputs data in straight binary format (Figure 10). Data is clocked out on the falling edge of the DCLK, MSB first. Serial Clock The external clock not only shifts data in and out, but it also drives the analog-to-digital conversion steps. BUSY pulses high for one clock period after the last bit of the control byte. Successive-approximation bit deci- sions are made and appear at DOUT on each of the next 12 DCLK falling edges. BUSY and DOUT go into a high-impedance state when CS goes high. The conversion must complete in 500µs or less; if not, droop on the sample-and-hold capacitors can degrade conversion results. Data Framing The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conver- sion starts on DCLK’s falling edge, after the eighth bit of the control byte is clocked into DIN. The first logic 1 clocked into DIN after bit 6 of a conver- sion in progress is clocked onto the DOUT pin and is treated as a START bit (Figure 8). Once a start bit has been recognized, the current con- version must be completed. The fastest the MXB7843 can run with CS held continu- ously low is 15 clock conversions. Figure 8 shows the serial-interface timing necessary to perform a conver- sion every 15 DCLK cycles. If CS is connected low and DCLK is continuous, guarantee a start bit by first clock- ing in 16 zeros. Most microcontrollers (µCs) require that data transfers occur in multiples of eight DCLK cycles; 16 clocks per conversion is typically the fastest that a µC can drive the MXB7843. Figure 9 shows the serial-interface timing nec- essary to perform a conversion every 16 DCLK cycles. 8-Bit Conversion The MXB7843 provides an 8-bit conversion mode selected by setting the MODE bit in the control byte high. In the 8-bit mode, conversions complete four clock cycles earlier than in the 12-bit output mode, resulting in 25% faster throughput. This can be used in conjunction with serial interfaces that provide 12-bit transfers, or two conversions could be accomplished with three 8-bit transfers. Not only does this shorten each conversion by 4 bits, but each conversion can also 2.375V to 5.25V, 4-Wire Touch-Screen Controller ______________________________________________________________________________________ 13 |
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