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LSM303DLMTR bảng dữ liệu(PDF) 33 Page - STMicroelectronics

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LSM303DLMTR bảng dữ liệu(HTML) 33 Page - STMicroelectronics

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LSM303DLM
Register description
Doc ID 018725 Rev 1
33/38
The D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized.
Duration time steps and maximum values depend on the ODR chosen.
9.2
Magnetic field sensing register description
9.2.1
CRA_REG_M (00h)
9.2.2
CRB_REG_M (01h)
Table 53.
INT2_DURATION_A description
D6 - D0
Duration value. Default value: 000 0000
Table 54.
CRA_REG_M register
0(1)
0(1)
1.
This bit must be set to ‘0’ for correct working of the device.
0(1)
DO2
DO1
DO0
0(1)
0(1)
Table 55.
CRA_REG_M description
DO2 to DO0
Data output rate bits. These bits set the rate at which data is written to all three data
output registers (refer to
Table 56). Default value: 100
Table 56.
Data rate configurations
DO2
DO1
DO0
Minimum data output rate (Hz)
00
0
0.75
00
1
1.5
01
0
3.0
01
1
7.5
10
0
15
10
1
30
11
0
75
1
1
1
220
Table 57.
CRA_REG register
GN2
GN1
GN0
0(1)
1.
This bit must be set to ‘0’ for correct working of the device.
0(1)
0(1)
0(1)
0(1)
CRA_REG description
GN1-0
Gain configuration bits. The gain configuration is common for all channels (refer to
Table 58)



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