LPC1111 datasheet(49/64 Pages) NXP

49 / 64 page

LPC1111_12_13_14

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Product data sheet

Rev. 5 — 22 June 2011

49 of 64

NXP Semiconductors

LPC1111/12/13/14

32-bit ARM Cortex-M0 microcontroller

[1]

Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the

main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),

and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).

[2]

Tamb = 40 C to 85 C.

[3]

Tcy(clk) = 12  Tcy(PCLK).

[4]

Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.

SPI slave (in SPI mode)

Tcy(PCLK)

PCLK cycle time

tDS

data set-up time

in SPI mode

[3][4]

tDH

data hold time

in SPI mode

[3][4]

 T

cy(PCLK) + 4

tv(Q)

data output valid time in SPI mode

[3][4]

 T

cy(PCLK) + 11

th(Q)

data output hold time in SPI mode

[3][4]

 T

cy(PCLK) + 5

Table 17.

Dynamic characteristics of SPI pins in SPI mode

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.

Fig 27. SPI master timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk)

tclk(H)

tclk(L)

tDS

tDH

tv(Q)

DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID

MOSI

MISO

tDS

tDH

DATA VALID

th(Q)

DATA VALID

tv(Q)

CPHA = 1

CPHA = 0

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