công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

STP1612PW05 bảng dữ liệu(PDF) 17 Page - STMicroelectronics

tên linh kiện STP1612PW05
Giải thích chi tiết về linh kiện  16-channel LED driver with 16-bit PWM, 8-bit gain and full LED error detection
PDF  35 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STP1612PW05 bảng dữ liệu(HTML) 17 Page - STMicroelectronics

Back Button STP1612PW05 Datasheet HTML 13Page - STMicroelectronics STP1612PW05 Datasheet HTML 14Page - STMicroelectronics STP1612PW05 Datasheet HTML 15Page - STMicroelectronics STP1612PW05 Datasheet HTML 16Page - STMicroelectronics STP1612PW05 Datasheet HTML 17Page - STMicroelectronics STP1612PW05 Datasheet HTML 18Page - STMicroelectronics STP1612PW05 Datasheet HTML 19Page - STMicroelectronics STP1612PW05 Datasheet HTML 20Page - STMicroelectronics STP1612PW05 Datasheet HTML 21Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 35 page
background image
STP1612PW05
Grey scales data loading
Doc ID 15819 Rev 4
17/35
8
Grey scales data loading
The STP1612PW05 is able to manage a gray-scale depth of 12 or 16 bits for each output,
exploiting an e-PWM algorithm.
The bit D of the configuration register is used to select the grey-scale loading. Its value can
be set to “0” for 12 bits or “1” for 16 bits. By default, D is set to “0”.
Loading of the data is performed through the serial input on a dedicated buffer and two
different methods can be used.
With both methods, the first incoming data packet is relative to the output 15; the following
packet is relative to the output 14 and so on up to the output 0.
If F=”0”, when a data packet has been loaded, the latch signal (LE) must become active for
one CLK cycle (data latch). When the last data packet, relative to the output 0, has been
loaded, the latch signal must be active for two CLK cycles (global latch) and all the data will
be transferred to the e-PWM registers starting from the MSB.
If F=”1” all data packets (12 or 16 bits x16) are loaded and then the global latch signal must
be active and all the data will be transferred to the e-PWM registers starting from the MSB.
Figure 7.
Full timing for data loading



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com