TS317CPRO datasheet(2/14 Pages) TSC

2 / 14 page

TS317

3-Terminal Adjustable Positive Voltage Regulator

2/14

Version: D07

Thermal Performance

Condition

Package type

Symbol

Typ

Unit

Thermal Resistance Junction to Air

TO-220

RΘJA

oC/W

TO-263

TO-252

100

SOT-223

130

Thermal Resistance Junction to Case

TO-220

RΘJC

oC/W

TO-263

TO-252

SOT-223

Electrical Characteristics

(VI -VO = 5.0 V, Io=500mA for TO-220/TO-263 packages, Io=200mA for TO-252/SOT-223 package)

Parameter

Figure

Symbol

Min.

Typ.

Max.

Unit

Reference voltage, 3V ≤ Vi-Vo ≤ 40V

10mA

≤ Io ≤ Imax, Pd ≤ Pmax,

Vref

1.20

1.25

1.30

Line regulation (Note 3)

Ta = 25

oC, 3V≤Vi-Vo≤40V

REGline

0.01

0.07

%/V

Load regulation Ta = 25

oC, 10mA ≤ I

O ≤ Imax (Note 2)

VO ≤ 5.0

VO ≥ 5.0

REGload

5.0

0.1

0.5

Thermal regulation, Ta = 25

oC (Note 5), 20mS Pulse

REGtherm

0.03

0.07

%Vo/W

Adjustment pin current

Iadj

100

Adjustment pin current change, 3V ≤ VI - VO ≤ 40V

10mA ≤ Io ≤ Imax, Pd ≤ Pmax,

1.2

∆Iadj

0.2

5.0

Maximum output current, VI - VO ≤ 15V, Pd ≤ Pmax

TO-220 / TO-263 Package

TO-252 / SOT-223 Package

Imax

1.5

0.5

Temperature stability (TLOW ≤ Tj ≤ THIGH)

% Vo

Minimum load current to maintain regulation

(VI - VO = 40 V)

ILmin

3.5

RMS Noise, % of VO, Ta =25

oC, 10Hz ≤ f ≤ 10KHz

0.003

% Vo

Ripple Rejection, Vo =10V, f =120Hz (Note 3)

Without Cadj

Cadj = 10uF

PSRR

Long-term stability (Note 4), Tj = 125ºC, 1000hrs

0.3

1.0

Notes: 1. TLOW to THIGH = 0

oC to +125oC, Pmax is internally limited

2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating

effects must be taken into account separately. Pulse testing with low duty cycle is used.

3. Cadj, when used, is connected between the adjustment pin and ground. Since Long-Term Stability cannot

be measured on each device before shipment, this specification is an engineering estimate of average

stability from lot to lot.

4. Power dissipation within an IC voltage regulator produces a temperature gradient on the die, affecting

individual IC components on the die. These effects can be minimized by proper integrated circuit design and

layout techniques. Thermal Regulation in the effect of these temperature gradients on the output voltage

and is expressed in the percentage of output change per watt of power change in a specified time.

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