L6728D datasheet(16/33 Pages) STMICROELECTRONICS

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Application details

L6728D

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Doc ID 16498 Rev 1

Application details

10.1

Compensation network

The control loop shown in Figure 5 is a voltage mode control loop. The output voltage is

regulated to the internal reference (when present, the offset resistor between the FB node

and GND can be neglected in control loop calculation).

The error amplifier output is compared to the oscillator sawtooth waveform to provide the

PWM signal to the driver section. The PWM signal is then transferred to the switching node

with VIN amplitude. This waveform is filtered by the output filter.

The converter transfer function is the small signal transfer function between the output of the

EA and VOUT. This function has a double pole at frequency FLC depending on the L-COUT

resonance and a zero at FESR depending on the output capacitor ESR. The DC gain of the

modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage

ΔV

OSC.

Figure 5.

PWM control loop

The compensation network closes the loop, joining the VOUT and EA output with transfer

function ideally equal to -Z

F/ZFB.

The compensation goal is to close the control loop while assuring high DC regulation

accuracy, good dynamic performance and stability. To achieve this, the overall loop needs

high DC gain, high bandwidth and good phase margin.

High DC gain is achieved by giving an integrator shape to the compensation network

transfer function. The loop bandwidth (F0dB) can be fixed by choosing the correct RF/RFB

ratio. However, for stability, it should not exceed FSW/2π. To achieve a good phase margin,

the control loop gain must cross the 0 dB axis with -20 dB/decade slope.

As an example, Figure 6 shows an asymptotic bode plot of a type III compensation.

OUT

ESR

OSC

ΔV

OSC

OUT

REF

PWM

COMPARATOR

ERROR

AMPLIFIER

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