L6726ATR datasheet(16/35 Pages) STMICROELECTRONICS

16 / 35 page

Application details

L6726A

16/35

Doc ID 12754 Rev 4

depending on the output capacitor ESR. The DC gain of the modulator is simply the input

voltage VIN divided by the peak-to-peak oscillator voltage ΔVOSC.

VOUT is scaled and transferred to FB node by the output resistor divider.

The compensation network closes the loop joining FB and COMP node with transfer

function ideally equal to -gm

·Z

Compensation goal is to close the control loop assuring high DC regulation accuracy, good

dynamic performances and stability. To achieve this, the overall loop needs high DC gain,

high bandwidth and good phase margin.

High DC gain is achieved giving an integrator shape to compensation network transfer

function. Loop bandwidth (F0dB) can be fixed choosing the right RF; however, for stability, it

should not exceed FSW/2π. To achieve a good phase margin, the control loop gain has to

cross 0 dB axis with -20 dB/decade slope.

As an example, Figure 9 shows an asymptotic bode plot of a type II compensation.

Figure 9.

Example of type II compensation.

●

Open loop converter singularities:

●

Compensation Network singularities frequencies:

Gain

[dB]

Log (Freq)

0dB

OTA

open loop

gain

closed loop

gain

compensation

gain

converter

open loop

gain

ESR

20log (gm·R

20log [V

IN/ΔVOSC·ROS/(RFB+ROS)]

0dB

π LC

OUT

⋅

----------------------------------

ESR

π C

OUT

ESR

⋅⋅

--------------------------------------------

π R

⋅⋅

------------------------------

π R

⋅

---------------------

⎝⎠

⎛⎞

⋅⋅

--------------------------------------------------

L6726ATR bảng dữ liệu(PDF) 16 Page - STMicroelectronics

L6726ATR bảng dữ liệu(HTML) 16 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

bảng dữ liệu tải về

Link URL