L6229Q datasheet(20/28 Pages) STMICROELECTRONICS

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Circuit description

L6229Q

20/28

Doc ID 15209 Rev 3

5.7

Non-dissipative overcurrent detection and protection

The L6229Q integrates an overcurrent detection circuit (OCD) for full protection. This circuit

provides output-to-output and output-to-ground short circuit protection as well. With this

internal over current detection, the external current sense resistor normally used and its

associated power dissipation are eliminated. Figure 19 shows a simplified schematic for the

overcurrent detection circuit.

To implement the over current detection, a sensing element that delivers a small but precise

fraction of the output current is implemented with each high side power MOS. Since this

current is a small fraction of the output current there is very little additional power

dissipation. This current is compared with an internal reference current IREF. When the

output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD

comparator signals a fault condition. When a fault condition is detected, an internal open

drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on.

The pin DIAG can be used to signal the fault condition to a

μC or to shut down the three-

phase bridge simply by connecting it to pin EN and adding an external R-C (see REN, CEN).

Figure 19.

Overcurrent protection simplified schematic

Figure 20 shows the overcurrent detection operation. The disable time tDISABLE before

recovering normal operation can be easily programmed by means of the accurate

thresholds of the logic inputs. It is affected whether by CEN and REN values and its

magnitude is reported in Figure 21. The delay time tDELAY before turning off the bridge when

an overcurrent has been detected depends only by CEN value. Its magnitude is reported in

Figure 22

CEN is also used for providing immunity to pin EN against fast transient noises. Therefore

the value of CEN should be chosen as big as possible according to the maximum tolerable

delay time and the REN value should be chosen according to the desired disable time.

The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended

values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs

disable time.

OVER TEMPERATURE

IREF

I1+I2 / n

I1 / n

HIGH SIDE DMOS

POWER SENSE

1 cell

POWER SENSE

1 cell

POWER SENSE

1 cell

POWER DMOS

n cells

POWER DMOS

n cells

POWER DMOS

n cells

HIGH SIDE DMOS

OUT1

OUT2

VSA

OUT3

VSB

I2/ n

I3/ n

OCD

COMPARATOR

TO GATE

LOGIC

INTERNAL

OPEN-DRAIN

RDS(ON)

Ω TYP.

CEN

REN

DIAG

VDD

μC or LOGIC

D02IN1381

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