PCF8593 datasheet(5/35 Pages) NXP

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PCF8593

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Product data sheet

Rev. 04 — 6 October 2010

5 of 35

NXP Semiconductors

PCF8593

Low power clock and calendar

7.3 Control and status register

The control and status register is defined as the memory location 00h with free access for

reading and writing via the I2C-bus. All functions and options are controlled by the

contents of the control and status register (see Figure 4).

Fig 4.

Control and status register

timer flag:

alarm flag:

alarm enable bit:

mask flag:

function mode:

hold last count flag:

logic 0:

logic 1:

stop counting flag:

logic 0:

logic 1:

321

MSB

LSB

013aaa382

memory location 00h

alarm disabled: flags toggle

alarm control register to disabled

(memory locations 08h to 0Fh

are free RAM space)

logic 1:

enable alarm control register

(memory location 08h is the

alarm control register)

logic 0:

read locations 05h to 06h

unmasked

logic 1:

read date and month count

directly

50 % duty factor

seconds flag if alarm enable bit

is logic 0

50 % duty factor

minutes flag if alarm enable bit

is logic 0

logic 0:

clock mode 32.768 kHz

clock mode 50 Hz

event-counter mode

test modes

store and hold last count in

capture latches

count

count pulses

stop counting, reset divider

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