MAX11040K datasheet(21/35 Pages) MAXIM

21 / 35 page

24-/16-Bit, 4-Channel, Simultaneous-Sampling,

Cascadable, Sigma-Delta ADCs

______________________________________________________________________________________

Data Rate Control Register

The Data Rate Control register controls the output data

period, which corresponds to the output data rate of

the ADC. The data period is controlled by both a

coarse (FSAMPC[2:0]) and a fine (FSAMPF[10:0])

adjustment (see Table 8).

The final data rate is derived by dividing the XIN clock

frequency by a divider value. The divider value is a

function of FSAMPC[2:0] and FSAMPF[10:0]:

Data Rate = fXINCLOCK/Divider

Divider = Coarse Cycle Factor x 384 + Fine Cycle

Factor x FSAMPF[10:0]

Note: Fractional results for the divider are rounded

down to the nearest integer. Coarse cycle factor and

fine cycle factor come from Table 8. The effect of

FSAMPF[10:0] in the formula has limitations as noted in

the table.

Examples of output data rate vs. FSAMPC[2:0] and

FSAMPF[10:0] are shown in Table 9. Table 10 shows

typical device performance for various data rate settings.

DIN

SCLK

DOUT

CASCOUT0

(CASCIN0 = 0)

DRDYOUT0

(DRDYIN0 = 0)

DRDYOUT1

CASCOUT1

DEVICE 0 DATA READY

DEVICE 0 AND DEVICE 1 DATA READY

24 CYCLES

CHANNEL 0

DEVICE 0

CHANNEL 1

DEVICE 0

CHANNEL 2

DEVICE 0

CHANNEL 3

DEVICE 0

CHANNEL 0

DEVICE 1

CHANNEL 1

DEVICE 1

CHANNEL 2

DEVICE 1

CHANNEL 3

DEVICE 1

24 CYCLES

DEVICE 1 TAKES OVER SPI BUS

Figure 11. 192-Bit Data Read Operation Diagram for Two Cascaded Devices

Table 7. Data Register (MAX11060) (continued)

BIT

NAME

DESCRIPTION

[31:29]

000

—

[28:26]

IC[2:0]

Device address tag. IC[2:0] starts with 000 for the device nearest the master.

[25:24]

Channel 2 address tag = 10

[23:8]

CH3DATA[15:0]

Channel 3 16-bit conversion result (two’s complement)

[7:5]

000

—

[4:2]

IC[2:0]

Device address tag. IC[2:0] starts with 000 for the device nearest the master.

[1:0]

Channel 3 address tag = 11

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