PIC24F04KA201 FAMILY

DS80474B-page 2

 2011 Microchip Technology Inc.

TABLE 2:

SILICON ISSUE SUMMARY

Module

Feature

Item

Number

Issue Summary

Affected

A1

Resets

BOR

1.

Inadvertent Reset when disabling/enabling BOR.

X

Core

Deep Sleep

2.

Failure to avoid Deep Sleep entry.

X

Comparator

—

3.

SPI

Enhanced

Buffer mode

4.

Errors when polling SPITBF flag.

X

Core

Low-Voltage

BOR

5.

LPBOR configuration results in ambiguous Resets.

X

Comparator

I/O Pins

6.

Enabling comparators disables some digital I/O ports.

X

Comparator

—

7.

Output polarity inversion also inverts edge-detect sensing.

X

Core

Doze mode

8.

Instruction execution glitches following DOZE bit changes.

X

Note 1:

Only those issues indicated in the last column apply to the current silicon revision.