PIC24F04KA201 datasheet(8/26 Pages) MICROCHIP

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PIC24FXXKA2XX

DS39991A-page 8

 2010 Microchip Technology Inc.

3.4

Flash Memory Programming in

ICSP Mode

3.4.1

PROGRAMMING OPERATIONS

The NVMCON register controls the Flash memory write

and erase operations. To program the device, set the

NVMCON register to select the type of erase operation

(see Table 3-2) or write operation (see Table 3-3). Set

the WR control bit (NVMCON<15>) to initiate the

program.

ICSP mode,

all programming operations are

self-timed. There is an internal delay between setting and

automatic clearing of the WR control bit when the

programming

operation

complete.

Refer

Section 5.0 “AC/DC Characteristics and Timing

Requirements” for information on the delays associated

with various programming operations.

3.4.2

STARTING AND STOPPING A

PROGRAMMING CYCLE

The WR bit (NVMCON<15>) is used to start an erase

or write cycle. Initiate the programming cycle by setting

the WR bit.

All erase and write cycles are self-timed. The WR bit

should be polled to determine if the erase or write cycle

is completed. Start a programming cycle as follows:

BSET

NVMCON, #WR

TABLE 3-3:

NVMCON VALUES FOR

WRITE OPERATIONS

TABLE 3-2:

NVMCON VALUES FOR

ERASE OPERATIONS

NVMCON

Value

Erase Operation

4064h

Erase the code memory and

Configuration registers (does not erase

programming executive code and

Device ID registers).

404Ch

Erase the general segment and

Configuration bits associated with it.

4068h

Erase the boot segment and

Configuration bits associated with it.

405Ah(1)

Erase four rows of code memory.

4059h(1)

Erase two rows of code memory.

4058h(1)

Erase a row of code memory.

4054h

Erase all the Configuration registers

(except the code-protect fuses).

4058h(1)

Erase Configuration registers except

FBS and FGS.

Note 1:

The destination address decides the

region (code memory or Configuration

NVMCON

Value

Write Operation

4004h(1)

Write one Configuration register.

4004h(1)

Program one row (32 instruction words)

of code memory or executive memory.

Note 1:

The destination address decides the

region (code memory or Configuration

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