CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

Document #: 38-06052 Rev. *M

Page 13 of 20

Notes

43. CE = HIGH for the duration of the above timing (both write and read cycle).

45. Semaphores are reset (available to both ports) at cycle start.

VALID ADRESS

VALID ADRESS

WRITE CYCLE

READ CYCLE

OE

R/W

SEM

Figure 10. Semaphore Read After Write Timing, Either Side[43]

MATCH

MATCH

Figure 11. Timing Diagram of Semaphore Contention[44, 45, 46]

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