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IP1844A bảng dữ liệu(PDF) 5 Page - Seme LAB

tên linh kiện IP1844A
Giải thích chi tiết về linh kiện  CURRENT MODE REGULATING PULSE WIDTH MODULATORS
PDF  6 Pages
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nhà sản xuất  SEME-LAB [Seme LAB]
Trang chủ  http://www.semelab.co.uk
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IP1844A bảng dữ liệu(HTML) 5 Page - Seme LAB

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For RT > 5kΩ,
1.8
Resultant frequency f
≈
(RTCT)
.0063 RT – 2.3
.0063 – 4
(
)
tc ≈ 0.55 RTCT
td ≈ RTCT Rn
1
Resultant frequency f =
(tc + td)
Oscillator timing capacitor CT is charged by VREF
through RT and discharged by an internal current source.
During the discharge time, the internal clock signal
blanks the output to the low state. Selection of RT and
CT therefore determines both oscillator frequency and
maximum duty cycle. Charge and discharge times are
determined by the formulae:
LAB
SEME
IP1844A SERIES
IP1845A SERIES
Semelab plc. Telephone (01455) 556565. Telex: 341927. Fax (01455) 552612.
Prelim. 2/95
Open–Loop Laboratory Test Fixture
APPLICATIONS INFORMATION
High peak current associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should
be connected close to pin 5 in a single point ground. The transistor and 5K potentiometer are used to sample the oscillator wave
form and apply an adjustable ramp to pin 3.
0.1
µF
1k
Ω
1kW
1k
Ω
ERROR AMP
ADJUST
4.7k
Ω
5k
Ω
ADJUST
4.7k
Ω
100k
Ω
2N2222
I
SENSE
R
T
C
T
0.1
µF
VREF
VCC
OUTPUT
GROUND
1
2
45
7
8
36
I
SENSE
VREF
VCC
O/P
GND
COMP
VFB
R
T /C T
Oscillator Waveforms and Maximum Duty Cycle
8
4
5
GND
R
T
C
T
REF
V
R
T C T
PIN4
V
(V
for 14 pin D package)
PIN7
INTERNAL CLOCK
INTERNAL CLOCK
OUTPUT – Max. Duty Cycle
PIN6
V
(V
for 14 pin D package)
PIN10
PIN4
V
(V
for 14 pin D package)
PIN7
OUTPUT – Max. Duty Cycle
PIN6
V
(V
for 14 pin D package)
PIN10
LARGE C
T
SMALL R
T
LARGE R
T
SMALL C
T



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