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LX1741CLM bảng dữ liệu(PDF) 7 Page - Microsemi Corporation |
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LX1741CLM bảng dữ liệu(HTML) 7 Page - Microsemi Corporation |
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7 / 15 page ![]() Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 Copyright © 2000 Rev. 1.1b, 2005-03-03 LX1741 High Efficiency High Voltage Boost Controller PRODUCTION DATA SHEET I N T E GRA T ED PR ODUC T S APPLI CATI ON I N FORMATI O N FUNCTIONAL DESCRIPTION The LX1741 is a Pulse Frequency Modulated (PFM) boost converter that is optimized for large step up voltage applications like LCD biasing. It operates in a pseudo- hysteretic mode with a fixed switch “off time” of 300ns. Converter switching is enabled when the feedback voltage, VFB, falls below the 1.29V reference or VADJ (see Block Diagram). When this occurs, comparator A activates the off-time controller. The off-time controller and the current limiter circuit activate comparator B which toggles the NDRV output circuit. The NDRV output is switched “on” (and remains “on”) until the inductor current ramps up to the peak current level. This current level is set via the external RCS resistor and monitored through the CS and SRC inputs. The load is powered from energy stored in the output capacitor during the inductor charging cycle. Once the peak inductor current value is achieved, the NDRV output is turned off (off-time is typically 300ns) allowing a portion of the energy stored in the inductor to be delivered to the load. This causes the output voltage to continue to rise at the input to the feedback circuit (i.e., comparator A). If the voltage at the FB input is still less than 1.29V at the end of the off-time period, the NDRV output switches the external FET “on” and the inductor charging cycle repeats until VFB is greater than the internal reference. This switching behavior is shown in Figure 9 and 11. The application of an external voltage source at the ADJ pin allows for output voltage adjustment over a typical range of approximately ±15%. The designer can select one of two possible methods. One option is to vary the reference voltage directly at the ADJ pin by applying a DC voltage from 0.9 to 1.5V. The second option is to connect a PWM logic signal to the ADJ pin (e.g., see Figure 2). The LX1741 includes an internal 50pF capacitor to ground that works with an external resistor to create a low-pass filter (i.e., filter out the AC component of a pulse width modulated input of fPWM ≥ 100KHz). The adjustment voltage level is selectable (with limited accuracy) by implementing the voltage divider created between the external series resistor and the internal 2.5MΩ resistor. If the DC voltage at the ADJ pin drops below 0.6V, the device will revert to the internal reference voltage level of 1.29V. A typical adjustment curve is shown in Figure 8 (see section titled: Characteristic Curves). Disabling the LX1741 is achieved by driving the SHDN pin with a low-level logic signal thus reducing the device power consumption to less than 1µA. OUTPUT VOLTAGE PROGRAMMING Selecting the appropriate values for R1 and R2 in the voltage divider connected to the feedback pin programs the output voltage. Using a value of 49.9K for R2 works well in most applications. R1 can be determined by the following equation (where VREF = 1.29V nominal): () V V - V R2 R1 REF REF OUT × = DESIGN EXAMPLE: Let R2 equals 49.9K and the required VOUT equal to 18V. () Ω = × Ω = K 4 . 646 49.9K R1 1.29V 1.29V - 18V INDUCTOR SELECTION AND CURRENT LIMIT PROGRAMMING Setting the level of peak inductor current to, at least, 1.5x the expected maximum DC input current will minimize the inductor size, the input ripple current, and the output ripple voltage. The designer is encouraged to use inductors that will not saturate at the peak inductor current level. An inductor value of 47µH is recommended. Choosing a lower value emphasizes peak current overshoot while choosing a higher value emphasizes output ripple voltage. The peak switch current is defined using a resistor placed between the CS terminal and ground and the IPEAK equation is: CS SCALE D IN MIN PEAK R I t L V I I ⎟⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎜ ⎝ ⎛ ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎜ ⎜ ⎝ ⎛ + + = The maximum IPEAK value is limited by the ISRC value (max. = 0.8ARMS). The minimum IPEAK value is defined when RCS is zero. A typical value for the minimum peak current (IMIN) at 25 oC is 145mA. The parameter tD is related to internal operation of comparator A. A typical value at 25oC is 620ns. A typical value of ISCALE at 25 oC is 31mA per KΩ. All of these parameters have an effect on the final IPEAK value. DESIGN EXAMPLE: Determine IPEAK where VIN equals 3.0V and RCS equals 4.02KΩ using nominal values for all other parameters. 4.02KΩ kΩ 31mA 620ns H 47 3.0V 145mA IPEAK × + × + = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ µ The result of this example yields a nominal IPEAK equal to 145mA + 39.6mA + 124.6ma = 309.2mA. |
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