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DRF1301 bảng dữ liệu(PDF) 3 Page - Microsemi Corporation |
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DRF1301 bảng dữ liệu(HTML) 3 Page - Microsemi Corporation |
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3 / 4 page ![]() DRF1301 The test circuit illustrated in Figure 2 was used to evaluate the DRF1301 (available as an evaluation board DRF13XX/EVALSW.) The input control signal is applied via IN and SG pins using RG188. This provides excellent noise immunity and control of the signal ground currents. The +V DD inputs (pins 2, 6, 8 and 12) should be heavily by-passed by 1uF capacitors as close to the pins as possible. The capacitors used for this function must be capable of supporting the RMS currents and frequency of the gate load. R L set for IDM at VDS max this load is used to evaluate the output performance. Figure 2, DRF1301 Test Circuit Figure 1, DRF1301 Circuit Diagram The DRF1301 is configured as a Push Pull Hybrid incorporating two independent channels configured with a common source each consisting of a driver, a high voltage MOSFET and by-pass capacitors. The function of the by-pass capacitors C1 and C2 is to reduce the internal parasitic loop inductance. This coupled with the tight geometry of the hybrid allows optimal gate drive to the MOSFET. This low parasitic approach coupled with the Schmitt trigger input (IN), Kelvin signal ground (SG) and the Anti-Ring function; provide improved stability and control in Kilowatt to Multi- Kilowatt high frequency applications. The IN pin should be referenced to the Kelvin Ground (SG) and is applied to a Schmitt Trigger. The SG pin is a Kelvin return for the IN pin only. The signal is then applied to the intermediate drivers and level shifters; this section contains proprietary circuitry designed specifically for ring abatement. To further increase the utility of the device the driver die and the MOSFET die are adjacent die selected. This provides a very close match in the turn on and propagation delays. |
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