Data Sheet

9

Rev 1.1, 2010-09-30

H-Bridge and Dual Half Bridge Driver IC

TLE7181EM

General Product Characteristics

The PWM frequency is limited by thermal constraints and the maximum duty cycle (minimum charging time of

bootstrap capacitor).

Note: Within the functional range the IC operates as described in the circuit description. The electrical

characteristics are specified within the conditions given in the related electrical characteristics table.

4.3

Thermal Resistance

Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go

to www.jedec.org.

4.4

Default State of Inputs

Table 2

Default State of Inputs (if left open)

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.

4.3.1

1) Not subject to production test, specified by design.

R

thJC

–

–5K/W

–

4.3.2

Junction to Ambient1)

R

thJA

–35

–

K/W

2)

2) Exposed Heatslug Package use this sentence: Specified

R

convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner

copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first

inner copper layer.

Characteristic

State

Remark

Default state of PWM and DIR

Low

Low side MOSFETs off and Highside

MOSFETs on

Default state of DT

OPEN

maximum deadtime

Default state of ENA

Low

Output stages disabled device in sleep

mode

Default state of SCDL

OPEN

Short circuit detection deactivation &

warning

Default state of DRVDIS

High

All output stages off & no error will be

reported