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ADG5213 bảng dữ liệu(PDF) 9 Page - Analog Devices

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ADG5213 bảng dữ liệu(HTML) 9 Page - Analog Devices

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ADG5212/ADG5213
Rev. 0 | Page 9 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1 1
D1 2
S1 3
VSS 4
IN2
16
D2
15
S2
14
VDD
13
GND 5
NC
12
S4 6
S3
11
D4 7
D3
10
IN4 8
IN3
9
NC = NO CONNECT
ADG5212/
ADG5213
TOP VIEW
(Not to Scale)
Figure 2. TSSOP Pin Configuration
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
2. NC = NO CONNECT.
1
S1
2
VSS
3
GND
4
S4
11 VDD
12 S2
10 NC
9S3
TOP VIEW
(Not to Scale)
ADG5212/
ADG5213
Figure 3. LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
15
IN1
Logic Control Input.
2
16
D1
Drain Terminal. This pin can be an input or an output.
3
1
S1
Source Terminal. This pin can be an input or an output.
4
2
VSS
Most Negative Power Supply Potential.
5
3
GND
Ground (0 V) Reference.
6
4
S4
Source Terminal. This pin can be an input or an output.
7
5
D4
Drain Terminal. This pin can be an input or an output.
8
6
IN4
Logic Control Input.
9
7
IN3
Logic Control Input.
10
8
D3
Drain Terminal. This pin can be an input or an output.
11
9
S3
Source Terminal. This pin can be an input or an output.
12
10
NC
No Connect. These pins are open.
13
11
VDD
Most Positive Power Supply Potential.
14
12
S2
Source Terminal. This pin can be an input or an output.
15
13
D2
Drain Terminal. This pin can be an input or an output.
16
14
IN2
Logic Control Input.
N/A1
EP
Exposed pad
Exposed Pad. The exposed pad is connected internally. For increased reliability of the
solder joints and maximum thermal capability, it is recommended that the pad be
soldered to the substrate, VSS.
1 N/A means not applicable.
Table 8. ADG5212 Truth Table
ADG5212 INx
Switch Condition
1
On
0
Off
Table 9. ADG5213 Truth Table
ADG5213 INx
S1, S4
S2, S3
0
Off
On
1
On
Off



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