MPC8548E datasheet(73/143 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

PCI Express

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the

TX UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in

the 3500 consecutive UI interval with a fit algorithm using a minimization

merit function (for example, least squares and median deviation fits).

Figure 48. Minimum Transmitter Timing and Voltage Output Compliance Specifications

17.4.3

Differential Receiver (RX) Input Specifications

Table 57 defines the specifications for the differential input at all receivers (RXs). The parameters are

specified at the component pins.

Table 57. Differential Receiver (RX) Input Specifications

Symbol

Parameter

Min

Nom

Max

Unit

Comments

Unit interval

399.88

400

400.12

Each UI is 400 ps ± 300 ppm. UI does not account

for spread spectrum clock dictated variations.

See Note 1.

VRX-DIFFp-p

Differential

peak-to-peak

input voltage

0.175

—

1.200

VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D–|. See Note 2.

VTX-DIFF = 0 mV

(D+ D– Crossing Point)

[De-Emphasized Bit]

0.07 UI = UI – 0.3 UI (JTX-TOTAL-MAX)

566 mV (3 dB) >=

VTX-DIFFp-p-MIN >= 505 mV (4 dB)

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

[Transition Bit]

VTX-DIFFp-p-MIN = 800 mV

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