IMX28CEC datasheet(18/70 Pages) FREESCALE

18 / 70 page

i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

Freescale Semiconductor

3.1.5

Power Modes

Table 21 describes the core, clock, and module settings for the different power modes of the processor.

3.1.6

Supply Power-Up/Power-Down Requirements

There is no special power-up sequence. After applying 5 V or battery in any order, the rest of the power

supplies are internally generated and automatically come up in a safe way.

There is no special power-down sequence. 5 V or the battery can be removed at any time.

3.1.7

Reset Timing

Because the i.MX28 is a PMU and an SoC, power-on reset is generated internally and there is no timing

requirement on external pins.

The i.MX28 can be reset by asserting the external pin RESETN for at least 100 mS and later deasserting

RESETN.

If the reset occurs while the device is only powered by the battery, then the reset kills all of the power

supplies and the system reboots on the assertion of PSWITCH. If auto-restart is set up ahead of time, the

system reboots immediately.

If the chip is powered by 5 V, then the reset serves to reset the digital sections of the chip. If the DCDC is

operating at the time of the reset, then power switches back to the default linear regulators powered by 5 V.

Figure 2. RESETN Timing

Table 21. Power Mode Settings

Core/Clock/Module

Deep-Sleep

Standby

Run

ARM Core

Off

USB0 PLL (System PLL)

Off

OSC24M

Off

OSC32K

DCDC

Off

RTC

Other Modules

Off

On/Off

RESETN

At least 100ms

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