16F1828 datasheet(98/419 Pages) MICROCHIP

98 / 419 page

PIC16(L)F1824/1828

DS41419B-page 98

Preliminary

 2010 Microchip Technology Inc.

8.5.6

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 8-6.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

U-0

OSFIF

C2IF(1)

C1IF

EEIF

BCL1IF

—

CCP2IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

OSFIF:

Oscillator Fail Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

bit 6

C2IF:

Comparator C2 Interrupt Flag bit(1)

= Interrupt is pending

= Interrupt is not pending

bit 5

C1IF:

Comparator C1 Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

bit 4

EEIF:

EEPROM Write Completion Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

bit 3

BCL1IF:

MSSP Bus Collision Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

bit 2-1

Unimplemented:

Read as ‘0’

bit 0

CCP2IF:

CCP2 Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

Note 1:

PIC16F/LF1828 only.

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