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RFHCS362G bảng dữ liệu(PDF) 22 Page - Microchip Technology |
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RFHCS362G bảng dữ liệu(HTML) 22 Page - Microchip Technology |
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22 / 54 page ![]() rfHCS362G/362F DS41189B-page 22 © 2011 Microchip Technology Inc. TABLE 4-3: CONFIG_1 4.5.5 GUARD The Guard time between code words can be set to 0 ms, 6.4 ms, 25.6 ms and 76.8 ms. If during a series of code words, the output changes from Hopping Code to Seed the Guard time will increase by 3 x TE. 4.5.6 TIMOUT[0..1] The transmission time-out can be set to 0.8 s, 3.2 s, 25.6 s or no time-out. After the time-out period, the encoder will stop transmission and enter a low power Shutdown mode. 4.5.7 DISC[0..9] The discrimination bits are used to validate the decrypted code word. The discrimination value is typi- cally programmed with the 10 Least Significant bits of the serial number or a fixed value. 4.5.8 OVR[0..1] The automatically incrementing synchronization coun- ter is at the core of generating the varying code. Since the counter is limited to 16 bits, it overflows after 65536 increments, after which the code hopping sequence repeats. In practice, this allows 20+ operations per day for ten years before repeating the sequence. In addi- tion, two overflow bits allow the sequence to be extended further. The feature is enabled by setting to logical “1” the two overflow bits OVL0 and OVL1. The overflow bits form part of the encrypted transmission, and therefore can be examined by receiver firmware. Table 4-4 shows how the overflow bits act when they are set to one during initial device configuration. TABLE 4-4: As can be seen from the table, the counter is effectively extended by one bit, that is OVL0. In addition, OVL1 provides indication of the second counter overflow. After the second overflow, OVL0 and OVL1 remain zero, providing permanent evidence of the first and second overflow events. Bit Address Field Description Values 0 DISC_0 Discrimination bits DISC [9:0] 1 DISC_1 2 DISC_2 ... ... 8 DISC_8 9 DISC_9 10 OVR_0 Overflow OVR [1:0] 11 OVR_1 12 XSER Extended Serial Number 0 - Disable 1 - Enable 13 SEEDC Seed Control 0 = Seed transmission on: S[3210] = 0001 (delay 1.6 s) S[3210] = 0101 (immediate) 1 = Seed transmission on: S[3210] = 0011 (delay 3.2 s) S[3210] = 1001 (immediate) 14 SEED_0 Seed options 00 - No Seed 01 - Limited Seed (Permanent and Delayed) 10 - Permanent and Delayed Seed 11 - Permanent Seed only 15 SEED_1 Sync. Counter OVL0 OVL1 No overflow 0-FFFFH 11 First overflow 2nd 0-FFFFH 01 Second overflow Third 0-FFFFH 00 Subsequent overflows 0 0 |
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