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R5F2138CMDFD bảng dữ liệu(PDF) 14 Page - Renesas Technology Corp

tên linh kiện R5F2138CMDFD
Giải thích chi tiết về linh kiện  The R8C/38M Group has data flash (1 KB 횞 4 blocks) with the background operation
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R8C/38M Group
2. Central Processing Unit (CPU)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01DS0082EJ0110 Rev.0.10
Page 14 of 55
Mar 04, 2011
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.



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