R5F562T7DDFM datasheet(79/94 Pages) RENESAS

79 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 79 of 92

Apr 20, 2011

RX62T Group

5. Electrical Characteristics

Note 1. The conversion time includes the sampling time and the comparison time. As the test conditions, the number of sampling states

is indicated.

Table 5.14

12-Bit A/D Conversion Characteristics

Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.

Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC

Ta = -40 to +85°C, ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz

Item

Min.

Typ.

Max.

Unit

Test Conditions

Resolution

Bit

Conversion time*1

(AD clock = 25-MHz operation)

2.0

s

Sampling 20 states

Analog input capacitance

Integral nonlinearity error

4.0

LSB

Offset error

7.5

LSB

Full-scale error

7.5

LSB

Quantization error

0.5

LSB

Absolute

accuracy

When a sample-and-hold circuit

is in use

8.0

LSB

AVin = 0.25 to AVREFH -

0.25

When a sample-and-hold circuit

is not in use

8.0

LSB

AVin = AVREFL to AVREFH

Permissible signal source impedance

3.0



Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. ICLK = 8 to 100 MHz, PCLK = 8 to 50 MHz.

Item

Min.

Typ.

Max.

Unit

Test Conditions

Resolution

Bit

Conversion time*1

(AD clock = 25-MHz operation)

1.0

s

Sampling 20 states

Analog input capacitance

Integral nonlinearity error

4.0

LSB

Offset error

7.5

LSB

Full-scale error

7.5

LSB

Quantization error

0.5

LSB

Absolute

accuracy

When a sample-and-hold circuit

is in use

8.0

LSB

AVin = 0.25 to AVREFH -

0.25

When a sample-and-hold circuit

is not in use

8.0

LSB

AVin = AVREFL to AVREFH

Permissible signal source impedance

3.0



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