©2011 Silicon Storage Technology, Inc.

S71417-03-000

02/11

21

2 Mbit SPI Serial Flash

SST25VF020B

Data Sheet

A Microchip Technology Company

Figure 18:Write Enable (WREN) Sequence

Write-Disable (WRDI)

The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any

new Write operations from occurring. The WRDI instruction will not terminate any programming opera-

instruction. CE# must be driven high before the WRDI instruction is executed.

Figure 19:Write Disable (WRDI) Sequence

Enable-Write-Status-Register (EWSR)

The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)

instruction and opens the status register for alteration. The Write-Status-Register instruction must be

executed immediately after the execution of the Enable-Write-Status-Register instruction. This two-

step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP

(software data protection) command structure which prevents any accidental alteration of the status

register values. CE# must be driven low before the EWSR instruction is entered and must be driven

high before the EWSR instruction is executed.

CE#

SO

SI

SCK

01 2 3 4 5 6 7

04

HIGH IMPEDANCE

MODE 0

MODE 3

1417 WRDI.0

MSB