LC876694B/78B/62B

No.6843-9/23

Port Output Configuration

Output configuration and pull-up/pull-down resistor options are shown in the following table.

Input /output is possible even when port is set to output mode.

Terminal

Option applies to: Options

Output Format

Pull-up resistor

Pull-down

resistor

1

CMOS

Programmable

(Note 1)

-

P00 to P07

1 bit units

2

15 voltage Nch-open drain

None

-

1

CMOS

Programmable

-

P10 to P17

each bit

2

Nch-open drain

Programmable

-

1

CMOS

Programmable

-

P30 to P37

each bit

2

15V Nch-open drain

None

-

P70

-

None

Nch-open drain

Programmable

-

P71 to P73

-

None

CMOS

Programmable

-

P80 to P87

-

None

Nch-open drain

None

-

1

High voltage Pch-open drain

-

Fixed

S0/T0 to S6/T6

each bit

2

High voltage Pch-open drain

-

None

S7/T7 to S15/T15

S16 to S31

-

None

High voltage Pch-open drain

-

fixed

1

High voltage Pch-open drain

-

Fixed

S32 to S47

each bit

2

High voltage Pch-open drain

-

None

S48 to S51

-

None

High voltage Pch-open drain

-

None

XT1

-

None

Input only

None

-

XT2

-

None

Output for 32.768kHz crystal

oscillation

None

-

Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07).

* Note 1: Connect as follows to reduce noise on VDD and increase the back-up time.

VSS1, and VSS2 must be connected together and grounded.

*Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the

VDD2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore,

when the VDD2 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and

the back up time becomes shorter because the through current runs from VDD to GND in the input buffer.

If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD

mode so that the port level becomes “L” level and unnecessary current consumption is prevented.

Back-up capacitors *2

Power

Supply

LSI

VDD1

VDD2

VDD3

VSS2

VSS1

VDD4

VFD

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