CYDM064B16

CYDM128B16

CYDM256B16

Document #: 001-00217 Rev. *H

Page 13 of 27

AC Test Loads and Waveforms

1.8V

GND

90%

90%

10%

10%

ALL INPUT PULSES

(a) Normal Load

R1

3.0V/2.5V/1.8V

OUTPUT

R2

C = 30 pF

OUTPUT

(b) Thévenin Equivalent (Load 1)

(c) Three-State Delay (Load 2)

R1

R2

3.0V/2.5V/1.8V

OUTPUT

≤ 3 ns

≤ 3 ns

including scope and jig)

3.0V/2.5V

1.8V

R1

R2

C = 30 pF

C = 5 pF

Notes

and 30 pF load capacitance.

26. Test conditions used are Load 3.

27. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy

waveform.

Over the Operating Range[23]

Parameter

Description

CYDM256B16, CYDM128B16, CYDM064B16

Unit

-55

Min

Max

Read Cycle

Read Cycle Time

55

ns

Address to Data Valid

55

ns

Output Hold From Address Change

5

ns

[24]

CE LOW to Data Valid

55

ns

OE LOW to Data Valid

30

ns

[25, 26, 27]

OE Low to Low Z

5

ns

[25, 26, 27]

OE HIGH to High Z

25

ns

[25, 26, 27]

CE LOW to Low Z

5

ns

[25, 26, 27]

CE HIGH to High Z

25

ns

[27]

CE LOW to Power up

0

ns

[27]

CE HIGH to Power down

55

ns

[24]

Byte Enable Access Time

55

ns

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