MPC5643L_11 datasheet(9/124 Pages) FREESCALE

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Introduction

MPC5643L Microcontroller Data Sheet, Rev. 6

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

— Four page-read buffers (each 128 bits wide) and a prefetch controller support speculative reading and optimized

flash access.

•

Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The buffers implement a

least-recently-used replacement algorithm to maximize performance.

•

Data flash (bank1) interface includes a 128-bit register to temporarily hold a single flash page. This logic supports

single-cycle read responses (0 AHB data-phase wait states) for accesses that hit in the holding register.

— No prefetch support is provided for this bank.

•

Programmable response for read-while-write sequences including support for stall-while-write, optional stall

notification interrupt, optional flash operation abort , and optional abort notification interrupt.

•

Separate and independent configurable access timing (on a per bank basis) to support use across a wide range of

platforms and frequencies.

•

Support of address-based read access timing for emulation of other memory types.

•

Support for reporting of single- and multi-bit error events.

•

Typical operating configuration loaded into programming model by system reset.

The platform flash controller is replicated for each processor.

1.6.8

Platform Static RAM Controller (SRAMC)

The SRAMC module is the platform SRAM array controller, with integrated error detection and correction.

The main features of the SRAMC provide connectivity for the following interfaces:

•

XBAR Slave Port (64-bit data path)

•

ECSM (ECC Error Reporting, error injection and configuration)

•

SRAM array

The following functions are implemented:

•

ECC encoding (32-bit boundary for data and complete address bus)

•

ECC decoding (32-bit boundary and entire address)

•

Address translation from the AHB protocol on the XBAR to the SRAM array

The platform SRAM controller is replicated for each processor.

1.6.9

Memory subsystem access time

Every memory access the CPU performs requires at least one system clock cycle for the data phase of the access. Slower

memories or peripherals may require additional data phase wait states. Additional data phase wait states may also occur if the

slave being accessed is not parked on the requesting master in the crossbar.

Table 2 shows the number of additional data phase wait states required for a range of memory accesses.

Table 2. Platform memory access time summary

AHB transfer

Data phase

wait states

Description

e200z4d instruction fetch

Flash memory prefetch buffer hit (page hit)

e200z4d instruction fetch

Flash memory prefetch buffer miss

(based on 4-cycle random flash array access time)

e200z4d data read

0–1

SRAM read

e200z4d data write

SRAM 32-bit write

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