AD9284 datasheet(21/24 Pages) AD

21 / 24 page

AD9284

Rev. 0 | Page 21 of 24

MEMORY MAP REGISTER DESCRIPTIONS

For more information about functions controlled in Register 0x00

to Register 0xFF, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

Voltage Reference (Register 0x18)

Bits[7:5]—Reserved

Bits[4:0]—Voltage Reference

Bits[4:0] scale the internally generated voltage reference and,

consequently, the full scale of the analog input. Within this register,

the reference driver can be configured to be more easily driven

externally by reducing the capacitive loading.

The relationship between the VREF voltage and the input full scale

is described by Equation 1. See Table 13 for a complete list of

Input_Full_Scale = VREF × 1.2

(1)

Table 13. VREF and Input Full Scale (Register 0x18)

Value

VREF (V)

Full Scale (V)

0x14

0.844

1.013

0x15

0.857

1.028

0x16

0.87

1.044

0x17

0.883

1.060

0x18

0.896

1.075

0x19

0.909

1.091

0x1A

0.922

1.106

0x1B

0.935

1.122

0x1C

0.948

1.138

0x1D

0.961

1.153

0x1E

0.974

1.169

0x1F

0.987

1.184

0x00

1.200

0x01

1.013

1.216

0x02

1.026

1.231

0x03

1.039

1.247

0x04

1.052

1.262

0x05

1.065

1.278

0x06

1.078

1.294

0x07

1.091

1.309

0x08

1.104

1.325

0x09

1.117

1.340

0x0A

1.13

1.356

0x0B

1.143

1.372

0x0C

1.156

1.387

0x0D

1.169

1.403

0x0E

1.182

1.418

0x0F

1.195

1.434

0x10

1.208

1.450

0x11

1.221

1.465

0x12

1.234

1.481

0x13

External

External x 1.2

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