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LC651154N bảng dữ liệu(PDF) 16 Page - Sanyo Semicon Device

tên linh kiện LC651154N
Giải thích chi tiết về linh kiện  Four-Bit CMOS Microcontrollers for Small-Scale Control Applications
PDF  39 Pages
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No. 6278-16/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter
Symbol
Conditions
Applicable pins
Ratings
Unit
and notes
min
typ
max
Pulse output function
tPCY
PE0
64
× TCYC
Period
High-level pulse width
tPH
PE0
32
× TCYC
±10%
µs
Low-level pulse width
tPL
PE0
32
× TCYC
±10%
Resolution
8
bit
Absolute precision
AV+ = VDD
±1
±2
LSB
AV– = VSS
When the A/D converter
72
312
speed is normal (1:1),
(TCYC =
(TCYC =
namely 26
× TCYC
2.77 µs)
12 µs)
Conversion time
TCAD
When the A/D converter
141
612
µs
speed is one half (1:2),
(TCYC =
(TCYC =
namely 51
× TCYC
2.77 µs)
12 µs)
Input reference voltage
AV+
AV+
AV–
VDD
V
AV–
AV–
VSS
AV+
Input reference current
IRIF
AV+ = VDD, AV– = VSS
AV+, AV–
200
500
800
µA
range
Analog input voltage
VAIN
AD0 to AD7
AV–
AV+
V
range
Including the output off
AD0 to AD7
1
leakage current.
(The I/O
VAIN = VDD
shared
Analog port input current
IAIN
function ports
µA
VAIN = VSS
have open-
–1
drain
specifications.)
Cw
When PE1 has the
WDR
0.1 ±5%
µF
open-drain specifications.
Recommended
Rw
When PE1 has the
WDR
680 ±1%
k
Ω
constants*10
open-drain specifications.
RI
When PE1 has the
WDR
100 ±1%
Ω
open-drain specifications.
Clear time (discharge)
tWCT
Figure 8
WDR
100
µs
Clear period (charge)
tWCCY
Figure 8
WDR
36
ms
Cw
When PE1 has the
WDR
0.047 ±5%
µF
open-drain specifications.
Recommended
Rw
When PE1 has the
WDR
680 ±1%
k
Ω
constants*10
open-drain specifications.
RI
When PE1 has the
WDR
100 ±1%
Ω
open-drain specifications.
Clear time (discharge)
tWCT
Figure 8
WDR
40
µs
Clear period (charge)
tWCCY
Figure 8
WDR
18
ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC.
2. The average over a 100 ms period.
3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby
state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle.
4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyo-
stipulated oscillator characteristics evaluation board.
5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option.
6. These are the results of testing using our (Sanyo’s) characteristics evaluation board with the recommended circuit constants used as external
components. The current flowing in the IC’s output transistors and transistors that have pull-up resistors is not included.
7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components.
8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range.
9. TCYC = 4
× the system clock period
10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and
adjacent pins and leakage associated with external resistors and capacitor is required during design.
VDD = 3 to 6 V
VDD = 3 to 6 V
VDD = 3 to 6 V
• Figure 7
• TCYC = 4 × system clock
period
• With an external resistor of
1 k
Ω and an external
capacitor of 50 pF on only
the n-channel open-drain
pins.



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