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LC35256DM bảng dữ liệu(PDF) 8 Page - Sanyo Semicon Device

tên linh kiện LC35256DM
Giải thích chi tiết về linh kiện  Dual Control Pins: OE and CE 256K (32768-word X 8-bit) SRAM
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LC35256DM bảng dữ liệu(HTML) 8 Page - Sanyo Semicon Device

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PS No. 5823-8/8
LC35256D-10, LC35256DM, DT-70/10
Notes on Circuit Design
Take the following operations into account when designing circuits that use these products to assure that none of the
items in the maximum ratings are exceeded.
• Supply voltage variations and fluctuations
• Manufacturing variations in the electrical characteristics of the electrical components, including semiconductor
devices, resistors, and capacitors.
• Ambient temperature
• Variations and fluctuations in the input and clock signals
• Possible application of abnormal pulses
Parameters listed in the allowable operating ranges must never exceed their stipulated ranges.
If input pins to a CMOS IC are left open, through currents may occur in internal circuits to which intermediate potentials
are input and result in incorrect circuit operation. Always verify that any unused pins are set up in appropriate states.
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Œ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Notes: 1. Reference value at Ta = 25°C, VCC = 3 V.
2. tRC: Read cycle time
Parameter
Symbol
Conditions
Ratings
Unit
min
typ*1
max
Data retention supply voltage
VDR
VCE ≥ VCC – 0.2 V
2.0
5.5
V
VCC = 3.0 V,
Ta
≤ 25°C
0.01
µA
Data retention current drain
ICCDR
VCE ≥ VCC – 0.2 V
Ta
≤ 60°C
0.7
µA
Ta
≤ 85°C
3.5
µA
Chip enable setup time
tCDR
0
ns
Chip enable hold time
tR
tRC*2
ns
Data Retention Characteristics at Ta = –40 to +85°C
Data Retention Waveforms
Note *: VCCL
5-V operation: 4.5 V
3-V operation: 2.7 V
Data retention mode



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