FM25Q32 datasheet(21/61 Pages) FIDELIX

21 / 61 page

preliminary(Aug.18.2010)

FM25Q32

11.2.6 Write Disable (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status

code “04h” into the DI pin and then driving /CS high. Note that the WEL bit is automatically reset

after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,

Block Erase and Chip Erase instructions.

/CS

CLK

Mode 0

Mode 3

Mode 0

Mode 3

Instruction (04 h)

High Impedance

/CS

CLK

Mode 0

Mode 3

Mode 0

Mode 3

Instruction (04 h)

High Impedance

Figure 6. Write Disable Instruction Sequence Diagram

11.2.7 Read Status Register-1 (05h) and Read Status Register-2 (35h)

The Read Status Register instructions allow the 8-bit Status Register to be read, The instruction is

entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 and “35h”

for Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then

shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in

figure 7. The Status Register bits are shown in figure 3a and 3b include the BUSY, WEL, BP2-BP0,

TB, SEC, SRP0, SRP1 and QE bits (see description of the Status Register earlier in this

datasheet).

The Status Register instruction may be used at any time, even while a Program, Erase, Write

Security Register or Write Status Register cycle is in progress. This allows the BUSY status bit to

be checked to determine when the cycle is complete and if the device can accept another

instruction. The Status Register can be read continuously, as shown in Figure 7. The instruction is

completed by driving /CS high.

Mode 0

Mode 3

Instruction(05h or 35h)

12 13

18 19

Status Register out

/CS

CLK

Status Register out

=MSB

Mode 0

Mode 3

Instruction(05h or 35h)

12 13

18 19

Status Register out

/CS

CLK

Status Register out

=MSB

Figure 7. Read Status Register Instruction Sequence Diagram

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