XMEGAD datasheet(21/309 Pages) ATMEL

21 / 309 page

8210B–AVR–04/10

XMEGA D

4.5

Data Memory

The Data memory contains the I/O Memory, internal SRAM, optionally memory mapped

EEPROM and external memory if available. The data memory is organized as one continuous

memory section, as shown in Figure 4-2 on page 22.

Figure 4-2.

Data Memory Map

I/O Memory, EEPROM and SRAM will always have the same start addresses for all XMEGA

devices. External Memory (if exist) will always start at the end of Internal SRAM and end at

address 0xFFFF.

4.6

Internal SRAM

The internal SRAM is mapped in the Data Memory space, always starting at hexadecimal

address location 0x2000. SRAM is accessed from the CPU by using the load (LD/LDS/LDD) and

store (ST/STS/STD) instructions.

4.7

EEPROM

XMEGA has EEPROM memory for non-volatile data storage. It is addressable either in as a sep-

arate data space (default), or it can be memory mapped and accessed in normal data space.

The EEPROM memory supports both byte and page access.

4.7.1

Data Memory Mapped EEPROM Access

The EEPROM address space can optionally be mapped into the Data Memory space to allow

highly efficient EEPROM reading and EEPROM buffer loading. When doing this EEPROM is

accessible using load and store instructions. Memory mapped EEPROM will always start at

hexadecimal address location 0x1000.

4.8

I/O Memory

The status and configuration registers for all peripherals and modules, including the CPU, are

addressable through I/O memory locations in the data memory space. All I/O locations can be

accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, transferring data

between the 32 general purpose registers in the Register File and the I/O memory. The IN and

Start/End

Address

I/O Memory

(Up to 4 KB)

EEPROM

(Up to 4 KB)

Internal SRAM

0x0000

0x1000

0xFFFF

0x2000

Data Memory

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