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FX980 bảng dữ liệu(PDF) 75 Page - CML Microcircuits

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FX980 bảng dữ liệu(HTML) 75 Page - CML Microcircuits

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TETRA Baseband Processor
FX980
© 1997 Consumer Microcircuits Limited
75
D/980/3
Operating Characteristics
For the following conditions unless otherwise specified:
MCLK Frequency = 9.216MHz, Symbol Rate = 18k bits/sec,
(VDD - VSS) = (VCC1 - VSS1) = (VCC2 - VSS2) = (VCC3 - VSSB) = (VDD1 - VSSA) = 3.0V to 3.6V for 3.3V
parameters, 4.5V to 5.5V, for 5.0V parameters. Tamb = - 40°C to +85°C.
At 5V, Bias/Ctrl = 0 and at 3.3V Bias/Ctrl = 1 in PowerDownCtrl register will optimise the analogue
performance in the Tx and Rx sections.
It is assumed that all powersave and clock stop bits are set, where appropriate.
Notes
Min.
Typ.
Max.
Units
5V DC Parameters (MCLK not toggled)
IDD (Tx powersaved)
1
20
mA
IDD (Rx powersaved)
1
20
mA
IDD (Aux powersaved)
1
34
mA
IDD (All powersaved)
1
<0.05
mA
IDD (Not powersaved)
1
36
mA
5V AC Parameters (MCLK at 9.216MHz)
IDD (Tx powersaved)
1
40
mA
IDD (Rx powersaved)
1
35
mA
IDD (Aux powersaved)
1
62
mA
IDD (All powersaved)
1
12
mA
IDD (Not powersaved)
1
64
mA
3.3V DC Parameters (MCLK not toggled)
IDD (Tx powersaved)
1
18
mA
IDD (Rx powersaved)
1
18
mA
IDD (Aux powersaved)
1
31
mA
IDD (All powersaved)
1
<0.05
mA
IDD (Not powersaved)
1
32
mA
3.3V AC Parameters (MCLK at 9.216MHz)
IDD (Tx powersaved)
1
31
mA
IDD (Rx powersaved)
1
33
mA
IDD (Aux powersaved)
1
48
mA
IDD (All powersaved)
1
7.5
mA
IDD (Not powersaved)
1
49
mA
MCLK Input
'High' pulse width
3
40
ns
'Low' pulse width
3
40
ns
Input impedance (at 100Hz)
10
M
Ω
Notes:
1.
Not including any current drawn from the device pins by external circuitry.
3.
Timing for an external input to the MCLK pin.



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