FX829P4 datasheet(10/34 Pages) CMLMICRO

10 / 34 page

Baseband Signal Processor

FX829

D/829/4

BIT 7

(D7)

BIT 6

(D6)

BIT 5

(D5)

BIT 4

(D4)

BIT 3

(D3)

BIT 2

(D2)

BIT 1

(D1)

BIT 0

D0)

CONTROL 1

CONTROL 2

CONTROL 3/IRQ ENABLE

AUDIO ATTENUATION

TXDATA

MOD LEVELS (1)

MOD LEVELS (2)

RX SYNC WORD (1)

RX SYNC WORD (2)

STATUS

RXDATA

X = undefined

CONTROL1 Register (Hex address $10)

This register is used to control the functions of the device as described below:

AMP1

(Bit 7)

When this bit is "1", AMP1 is enabled.

When this bit is "0", AMP1 is disabled (i.e. powersaved).

AMP2

(Bit 6)

When this bit is "1", both AMP2 and MOD2 are enabled.

When this bit is "0", both AMP2 and MOD2 are disabled (i.e. powersaved) and the

MOD2 output is pulled to VBIAS via a 1MW resistor.

AUDIO

(Bit 5)

When this bit is "1", the audio filter/limiter section is enabled.

When this bit is "0", the audio filter/limiter section is disabled (i.e. powersaved).

FFSKRX

(Bit 4)

When this bit is "1", the FFSK Rx is enabled.

When this bit is "0", the FFSK Rx is disabled (i.e. powersaved).

Note:

The FFSK Rx and Tx cannot both be enabled at the same time. If both

FFSKRX and FFSKTX are "1", then they will both be disabled

(i.e. powersaved).

FFSKTX

(Bit 3)

When this bit is "1", the FFSK Tx is enabled.

When this bit is "0", the FFSK Tx is disabled (i.e. powersaved).

Note:

The FFSK Tx and Rx cannot both be enabled at the same time. If both

FFSKTX and FFSKRX are "1", then they will both be disabled

(i.e. powersaved).

The DTMF Encoder and FFSK Tx cannot both be enabled at the same time.

If both DTMFEN and FFSKTX are "1", then they will both be disabled.

UK/F

(Bit 2)

When this bit is "1", the SYNC/SYNT is set to the PAA standard of

"1011010000110011" (SYNC)

When this bit is "0", the SYNC/SYNT is set to the MPT standard of

"1100010011010111" (SYNC)

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