CTCSS/DCS/SELCALL Processor

FX828

© 2009 CML Microsystems Plc

11

D/828/4

SIGNALLING SET-UP Register (Hex address $82)

This register is used to define the signalling parameters, as described below:

TONE DECODER

BANDWIDTH

(Bits 7, 6, 5 and 4)

These four bits set the bandwidth of the CTCSS/Selcall tone decoder according

to the table below:

BANDWIDTH

Bit 7

Bit 6

Bit 5

Bit 4

Will Decode

Will Not Decode

Recommended for CTCSS

1

0

0

0

±1.1%

±2.4%

Recommended for CCIR

1

0

0

1

±1.3%

±2.7%

1

0

1

0

±1.6%

±2.9%

1

0

1

1

±1.8%

±3.2%

1

1

0

0

±2.0%

±3.5%

1

1

0

1

±2.2%

±3.7%

Recommended for ZVEI

1

1

1

0

±2.5%

±4.0%

1

1

1

1

±2.7%

±4.2%

FAST CTCSS MODE

(Bit 3)

When CTCSS FAST DETECT ENABLE (Bit 5 SIGNALLING CONTROL

Register, $80) is "1", this bit selects the FAST CTCSS DETECT or the FAST

CTCSS PREDICTIVE mode, according to the table below:

DETECT/

PREDICTIVE

Bit 3

Function

0

DETECT mode

1

PREDICTIVE mode

If the CTCSS FAST DETECT ENABLE bit is "0" then both modes are

deselected.

TONE DECODER

MODE

(Bit 2)

When this bit is "1" the CTCSS/Selcall tone decoder is set to detect inband

(Selcall) tones. When this bit is "0" the tone decoder is set to detect subaudio

(CTCSS) tones.

SUBAUDIO TX MODE

(Bit 1)

When this bit is "1" the subaudio transmitter will be set to transmit DCS signals,

if enabled. When this bit is "0" the subaudio transmitter will be set to transmit

CTCSS signals, if enabled.

DCS 23/24

(Bit 0)

When this bit is "1" the DCS transmitter and decoder are configured for a 23-bit

code. When this bit is "0" they are configured for a 24-bit code.

DCS BYTE 3 Register (Hex address $85)

DCS BYTE 2 Register (Hex address $86)

DCS BYTE 1 Register (Hex address $87)

These three bytes set the code that is transmitted or received in the DCS mode. The LSB bit 0 of the

DCS BYTE 1 is transmitted first and the last bit is the MSB bit 23 of DCS BYTE 3 in the 24-bit mode or bit

22 in the 23-bit mode.