CTCSS Signalling Processor

FX818

© 1997 Consumer Microcircuits Limited

11

D/818/4

GENERAL PURPOSE TIMER (GPT) Register (Hex address $8B)

This register is used to preset the value of a countdown timer. Once a binary value has been loaded into this

register, it will be automatically transferred to an internal register within the timer. This internal register is then

decremented at each count interval (1ms) until it reaches zero. On reaching zero, the GPT IRQ FLAG in the

IRQ FLAG Register (Hex address $8F) is set to "1". An interrupt is generated on the IRQN pin if the GPT IRQ

MASK in the IRQ MASK Register (Hex address $8E) is "1" otherwise the GPT IRQ FLAG remains set to "1"

and no interrupt is generated.

When the internal register has reached a count of zero, the action of the timer depends on the setting of the

TIMER RE-CYCLE bit in the GENERAL CONTROL Register (Hex address $88). If the TIMER RE-CYCLE bit

is "1" then the timer will re-load the countdown value from the GENERAL PURPOSE TIMER Register and

restart the countdown from this value. If the TIME RE-CYCLE bit is "0" then the timer will stop and no further

action or timer interrupts will take place until the GENERAL PURPOSE TIMER Register is re-loaded. Loading

the GENERAL PURPOSE TIMER with "0" will cause the timer circuitry to be disabled (i.e. powersaved).

IRQ MASK Register (Hex address $8E)

This register is used to control the interrupts (IRQs) as described below:

(Bits 7, 5, 4, 1 and 0)

Reserved for future use. These should be set to "0".

GPT IRQ MASK

(Bit 6)

When this bit is set to "1" it enables an interrupt that occurs when GPT IRQ

FLAG (Bit 6, IRQ FLAG Register, $8F) changes from "0" to "1". When this

bit is "0" the interrupt is masked.

CTCSS IRQ MASK

(Bit 3)

When this bit is set to "1" it enables an interrupt that occurs when CTCSS

IRQ FLAG (Bit 3, IRQ FLAG Register, $8F) changes from "0" to "1". When

this bit is "0" the interrupt is masked.

CTCSS FAST IRQ

MASK

(Bit 2)

When this bit is set to "1" it enables an interrupt that occurs when CTCSS

FAST IRQ FLAG (Bit 2, IRQ FLAG Register, $8F) changes from "0" to "1".

When this bit is "0" the interrupt is masked.

CTCSS TX/FAST RX FREQUENCY Register (Hex address $83)

This is a 16-bit register. Byte (1) is sent first. When the CTCSS fast detector is enabled, the bits 0 to 12 define

the receive frequency the fast predictive detector is looking for according to the formula below.

When the CTCSS transmitter is enabled, the bits 0 to 12 control the frequency of the transmitted CTCSS tones

according to the formula below.

When the fast detector and the transmitter are both enabled, the bits 0 to 12 define the receive frequency the

fast predictive detector is looking for and the frequency of the transmitted tone according to the formula below

(i.e. Tx tone = predictive tone).

A

f

(Hz)

16 x f

(Hz)

XTAL

TONE

=

where A is the binary number programmed into the 13 bits.