CMX625P4 datasheet(30/34 Pages) CMLMICRO

30 / 34 page

ISDN TA POTS Interface

CMX625

 2001 Consumer Microcircuits Limited

D/625/2

Tx Output Buffer

Notes

Min.

Typ.

Max.

Unit

Buffer output signal swing;

2.2

Vp-p

Load greater than 500

Ω

Power-Up Timing

Notes

Min.

Typ.

Max.

Unit

Device reset to reliable signal at TXO, TXON,

50.0

RING, SPM or TONEFSK output pins

Notes:

At 25

°C, not including any current drawn from the CMX625 pins by external circuitry.

At nominal signal frequencies and without skew.

Excluding IOM-2 serial bus interface pins: FSC, DCL, DD and DU in bus reversal.

At VDD = 5.0V, load resistance greater than 40kΩ, signal levels are proportional to VDD.

Frequency above 300Hz.

Referenced to DTMF tone of lower amplitude.

Bandwidth limited: 0 to 3.4kHz Gaussian Noise.

See filter response, Figure 12.

SPM has a soft rise and fall time of about 4ms. The level changes between VBIAS and

0dBm in 2dB steps, 16 steps per rise and fall. When SPM is disabled, an extra 4ms

falling tail end of signal should be taken into consideration.

10. Over the range VDD = 3.3V to 5.5V at Tamb = 25°C.

11. Represents a psophometrically weighted measurement.

12. For each of the TXON (if enabled) and TXO pins, load placed between the pin and

VDD / 2, for VDD = 5.0V only.

13. Derate linearly minimum TTL Logic ‘0’ level from 0.8V at Vdd = 3.3V to 0.5V at

Vdd = 2.7V.

14. All outputs CMOS levels.

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