iC-ML

HALL Position Sensor / Encoder

Rev A3, Page 4/17

ELECTRICAL CHARACTERISTICS

Operating conditions: VDD = 5 V ±10 % , Tj = -40 ... 125 °C, unless otherwise noted

Item

Symbol

Parameter

Conditions

Unit

No.

Min.

Typ.

Max.

General

001

VDD

Supply voltage

4.5

5

5.5

V

002

I(VDD)

Supply current

open pins, normal operation

14

20

mA

open pins, power reduction mode (PRM)

7

10

mA

003

I(VDD)sb

Standby supply current

NEN = VDD

200

µA

004

td(VDD)on Turn on delay

VDD > 4 V, see Fig. 9

10

µs

005

td(VDD)off Turn off delay

VDD < 2.6 V

10

µs

Hall sensor array

101

Hext

Requiered external magnetic field

strength

at chip surface

20

50

100

kA/m

102

psens

Hall sensor array pitch

see Fig. 1

1.28

mm

103

ysens

Hall sensor array distance to

center of die

see Fig. 1

0.7

mm

104

xdis

Lateral displacement of chip to

package

in TSSOP20 package, see Fig. 2

-0.2

0.2

mm

105

ydis

Vertical displacement of chip to

package

in TSSOP20 package, see Fig. 2

-0.2

0.2

mm

106

Φ

dis

Angular displacement of chip with

reference to package

in TSSOP20 package, see Fig. 2

-3

3

DEG

107

hsens

Distance chip surface to top of

package

in TSSOP20 package, see Fig. 2

400

µm

Signal conditioning

201

Voff

Offset voltage

on output, with external magnetic field ampli-

tude of 20 kA/m

-50

50

mV

202

TC(Voff)

Temperatur coefficient of offset

voltage

-50

50

µV/K

203

Vdc

Output mean value

45

50

55

%VDD

204

Ratio

Amplitude ratio of SIN / COS

0.95

1.00

1.05

205

fhc

Cut off frequency

20

kHz

206

t()settle

Settling time

to 70 % amplitude, Hext = 40 kA/m

80

150

µs

207

V()gain

Gain output voltage

0.05

4.0

V

208

V()ampl

Sine/Cosine amplitude

V()ampl = V()max - Vdc

0.9

1.0

1.1

V

Sine-to-digital converter

301

AArel

Relative angular error

with reference to one periode, see Fig. 3

-20

20

%

302

f(OSC)

Oscillator frequency

200

256

300

kHz

303

TC(OSC)

Temperature coefficient of oscilla-

tor frequency

-0.1

%/K

304

hys

Converter hysteresis

1

LSB

Configuration inputs CFG1, CFG2, CFG3

401

Vt()hi

Threshold voltage high

60

78

% VDD

402

Vt()lo

Threshold voltage low

25

40

% VDD

403

V0()

Open circuit voltage

43

57

% VDD

404

Ri()

Input resistance

45

150

450

kΩ

Enable input NEN

501

Vt()hi

Threshold voltage high

2

V

502

Vt()lo

Threshold voltage low

0.8

V

503

Vt()hys

Hysteresis

Vt()hys = Vt()hi - Vt()lo

300

mV

504

Ipu()

Pull-up current

V() = 0...VDD - 1 V

-240

-120

-25

µA

Digital outputs: A, B, C, D

601

Vs()hi

Saturation voltage high

Vs()hi = VDD - V(), I() = -4 mA

0.4

V

602

Vs()lo

Saturation voltage low

I() = 4 mA

0.4

V

603

tr()

Rise time

CL() = 50 pF

60

ns