TN805 datasheet(4/12 Pages) STMICROELECTRONICS

4 / 12 page

Characteristics

TN805, TN815, TS820, TYN608, TYN808, TYN1008

4/12

Doc ID 7476 Rev 6

Figure 3.

Average and DC on-state current

versus ambient temperature

(DPAK)

Figure 4.

Relative variation of thermal

impedance junction to case versus

pulse duration

100

125

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

(A)

T(AV)

(°C)

amb

α = 180°

D.C.

Recommended pad layout,

FR4 printed circuit board

1E-3

1E-2

1E-1

1E+0

0.1

0.2

0.5

1.0

K=[Z

th(j-c)

th(j-c)]

t (s)

Figure 5.

Relative variation of thermal

impedance junction to ambient

versus pulse duration (DPAK)

Figure 6.

Relative variation of gate trigger

current and holding current versus

junction temperature for TS820

1E-2

1E-1

1E+0

1E+1

1E+2

5E+2

0.01

0.10

1.00

K=[Z

th(j-a)

th(j-a)]

t (s)

DPAK

TO-220AB / IPAK

Recommended pad layout,

FR4 printed circuit board

-40

-20

100

120

140

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

T (°C)

I,I ,I [T ] /

GTHL

,I ,I [T =25°C]

GTHL

IGT

IH & I

= 1k

Figure 7.

Relative variation of gate trigger

and holding current versus junction

temperature

Figure 8.

Relative variation of holding

current versus gate-cathode

resistance (typical values)

-40

-20

100

120

140

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

T (°C)

I,I ,I [T ] /

GTHL

,I ,I [T =25°C]

GTHL

IGT

IH & IL

TN8 and TYNx8

1E-2

1E-1

1E+0

1E+1

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

R(k )

I [R

] / I [

=1k ]

HGK

RGK

Tj = 25°C

TS8

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