High-Frequency, High-Power, Low-Noise,

Step-Up DC-DC Converter

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13

Layout Considerations

Due to high inductor current levels and fast switching

waveforms, proper PC board layout is essential. Protect

sensitive analog grounds by using a star ground config-

uration. Connect PGND, the input bypass capacitor

ground lead, and the output filter capacitor ground lead

to a single point (star ground configuration). In addition,

minimize trace lengths to reduce stray capacitance and

trace resistance, especially from the LX pins to the catch

diode (D1) and output capacitor (C2) to PGND pins. If an

external resistor-divider is used to set the output voltage

(Figure 4), the trace from FB to the resistors must be

extremely short and must be shielded from switching

signals, such as CLK or LX. To optimize package power

dissipation and minimize device heating under heavy

loads, expand PC trace area connected to the three

PGND pins as much as the layout can allow. This is best

accomplished with a large PGND plane on the surface of

the board. Also note that outer-layer ground plane area

beneath the device provides little heat-sinking benefit. If

an outer-layer ground plane is not feasible, the PGND

pins should be connected to the inner-layer ground

plane with multiple vias (at least three vias per pin is rec-

ommended). Since the purpose of these vias is to opti-

mize thermal conductivity to the inner ground plane, be

sure that the vias have no gaps in their connections to

the ground plane. Refer to a layout example in the

MAX1708EVKIT data sheet.

___________________ Chip Information

SUBSTRATE: GND

PROCESS: BiCMOS

Package Information

For the latest package outline information and land patterns,

“-” in the package code indicates RoHS status only. Package

drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

PACKAGE

TYPE

PACKAGE

CODE

OUTLINE

NO.

LAND

PATTERN NO.

16 QSOP

E16+1

21-0055

90-0167