MSC8252 datasheet(26/68 Pages) FREESCALE

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MSC8252 Dual-Core Digital Signal Processor Data Sheet, Rev. 3

Electrical Characteristics

Freescale Semiconductor

2.5.1.2

DDR3 (1.5V) SDRAM DC Electrical Characteristics

Table 7 provides the recommended operating conditions for the DDR SDRAM controller when interfacing to DDR3 SDRAM.

Note:

At recommended operating conditions (see Table 3) with VDDDDR =1.5 V.

2.5.1.3

DDR2/DDR3 SDRAM Capacitance

Table 8 provides the DDR controller interface capacitance for DDR2 and DDR3 memory.

Note:

At recommended operating conditions (see Table 3) with VDDDDR = 1.8 V for DDR2 memory or VDDDDR =1.5 V for

DDR3 memory.

Table 7. DDR3 SDRAM Interface DC Electrical Characteristics

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O reference voltage

MVREF

0.49

× VDDDDR

0.51

× VDDDDR

V2,3,4

Input high voltage

VIH

MVREF + 0.100

VDDDDR

Input low voltage

VIL

GND

MVREF – 0.100

I/O leakage current

IOZ

–50

μA6

Notes:

VDDDDR is expected to be within 50 mV of the DRAM VDD at all times. The DRAM and memory controller can use the same or

different sources.

MVREF is expected to be equal to 0.5 × VDDDDR and to track VDDDDR DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±1% of the DC value.

VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF with a minimum value of MVREF – 0.4 and a maximum value of MVREF + 0.04 V. VTT should track variations

in the DC-level of MVREF.

The voltage regulator for MVREF must be able to supply up to 250 μA.

Input capacitance load for DQ, DQS, and DQS signals are available in the IBIS models.

Output leakage is measured with all outputs are disabled, 0 V

≤ V

OUT

≤ V

DDDDR.

Table 8. DDR2/DDR3 SDRAM Capacitance

Parameter

Symbol

Min

Max

Unit

Notes

I/O capacitance: DQ, DQS, DQS

CIO

1, 2

Delta I/O capacitance: DQ, DQS, DQS

CDIO

—

0.5

1, 2

Notes:

This parameter is sampled. VDDDDR = 1.8 V ± 0.1 V (for DDR2), f = 1 MHz, TA = 25°C, VOUT = VDDDDR/2,

VOUT (peak-to-peak) = 0.2 V.

This parameter is sampled. VDDDDR = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA = 25°C, VOUT = VDDDDR/2,

VOUT (peak-to-peak) = 0.175 V.

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