MSC8156E datasheet(39/68 Pages) FREESCALE

tên linh kiện	MSC8156E

Giải thích chi tiết về linh kiện	Six-Core Digital Signal Processor with Security

PDF	68 Pages

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Electrical Characteristics

MSC8156E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0

Freescale Semiconductor

Figure 12 shows the DDR SDRAM output timing diagram.

Figure 13 provides the AC test load for the DDR2 and DDR3 controller bus.

2.6.1.3

DDR2 and DDR3 SDRAM Differential Timing Specifications

This section describes the DC and AC differential timing specifications for the DDR2 and DDR3 SDRAM controller interface.

Figure 14 shows the differential timing specification.

Note:

VTR specifies the true input signal (such as MCK or MDQS) and VCP is the complementary input signal (such as

MCK or MDQS).

Figure 12. DDR SDRAM Output Timing

Figure 13. DDR2 and DDR3 Controller Bus AC Test Load

Figure 14. DDR2 and DDR3 SDRAM Differential Timing Specifications

ADDR/CMD

tDDKHAS, tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]

MDQS[n]

MCK[n]

tMCK

tDDKLDX

tDDKHDX

tDDKHAX ,tDDKHCX

Write A0

NOOP

tDDKHME

tDDKHMP

Output

Z0 = 50 Ω

RL = 50 Ω

VDDDDR/2

VTR

VCP

GND

GVDD

VOX or VIX

GVDD/2

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