PCKEL14PW datasheet(6/15 Pages) NXP

6 / 15 page

Philips Semiconductors

PCKEL14

2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip

Product data

Rev. 01 — 14 October 2002

6 of 15

9397 750 09564

[1]

Devices are designed to meet the DC speciﬁcations shown in this table, after thermal equilibrium has been established. The circuit is in

a test socket or mounted on a printed circuit board and transverse air ﬂow greater than 500 LFPM is maintained.

[2]

Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.

[3]

Outputs are terminated through a 50

Ω resistor to V

CC − 2V.

[4]

VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the

differential input signal. Normal operation is obtained if the HIGH level falls within the speciﬁed range and the peak-to-peak voltage lies

between Vp-p(min) and 1 V.

Table 6:

Positive DC characteristics[1]

VCC = 3.3 V; VEE =0V [2]

Symbol

Parameter

Conditions

Tamb = −40 °C

Tamb = +25 °C

Tamb = +85 °C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

IEE

power supply current

VOH

HIGH-level output

voltage

[3]

2125 2260 2420 2235 2345 2420 2275 2345 2420 mV

VOL

LOW-level output

voltage

[3]

1470 1605 1745 1490 1595 1680 1490 1595 1680 mV

VIH

HIGH-level input

voltage

single-ended

2110 -

2420 2135 -

2420 mV

VIL

LOW-level input

voltage

single-ended

1490 -

1825 1490 -

1825 mV

VBB

output voltage

reference

1.87

2.05

1.95

2.05

1.95

2.11

VIHCMR

HIGH-level input

voltage, common

mode range

(differential)

Vp-p < 500 mV [4]

1.3

2.9

1.2

2.9

1.2

2.9

Vp-p ≥ 500 mV

1.5

2.9

1.4

2.9

1.4

2.9

IIH

HIGH-level input

current

150

µA

IIL

LOW-level input

current

CLK

−300 -

µA

others

0.5

µA

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