LM3450 datasheet(21/28 Pages) NSC

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PRIMARY BIAS SUPPLY

The LM3450 requires a supply voltage at V

CC, not to exceed

25V. The device has V

CC under-voltage lockout (UVLO) with

rising and falling thresholds of 12.9V and 7.9V respectively.

A 24V Zener diode should be placed from the V

CC pin to GND

to protect the device from substantial spikes that could cause

damage.

Figure 18 shows how the LM3450 provides a quick way to

generate the necessary primary bias supply at start-up. Since

the AC line peak voltage is always higher than the rating of

the controller, all designs require an N-channel MosFET

(passFET). The passFET (Q

PS) is connected with its drain at-

tached to the rectified AC. The gate of Q

PS is connected to

the BIAS pin which has a stack of 2 Zener diodes internal to

the device. These diodes are then biased from the rectified

AC line through series resistance (R

BS). The source of QPS is

held at a V

GS below the Zener voltage and current flows

through Q

PS to charge up whatever capacitance is present. If

the capacitance is large enough, the source voltage will re-

main relatively constant over the line cycle and this becomes

the input bias supply at V

CC.

This bias circuit enables instant turn-on. However, once the

circuit is operational it is desirable to bootstrap V

CC to an aux-

iliary winding of the inductor or transformer (also used for

ZCD). The two bias paths are each connected to V

CC through

a diode to ensure the higher of the two is providing V

CC cur-

rent. This bootstrapping greatly improves efficiency when

quick start-up is necessary.

To ensure that the auxiliary winding is powering V

CC at all

times except start-up, the LM3450 has a dual BIAS mode. The

BIAS voltage at startup is 20V through two Zener diodes.

When the V

CC UVLO rising threshold is exceeded and the

device turns on, the BIAS pin voltage is reduced to 14V (bot-

tom 6V Zener is shorted). Once the V

CC UVLO falling thresh-

old is reached again, the BIAS pin will return to 20V to attempt

to restart the device.

It should be noted that the large hysteresis of V

CC UVLO and

the dual BIAS mode allow for a large variation of the auxiliary

bias circuitry easing the design of the magnetics.

30127439

FIGURE 18. Primary Bias Circuitry

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