PCA85232DA datasheet(5/54 Pages) NXP

5 / 54 page

PCA85232

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 8 December 2010

5 of 54

NXP Semiconductors

PCA85232

LCD driver for low multiplex rates

6.2 Pin description

[1]

For most applications SDA and SDAACK are shorted together (see Section 12.2).

[2]

The substrate (rear side of the die) is connected to VSS and should be electrically isolated.

Table 3.

Pin description

Symbol

Description

SDAACK[1]

1 to 3

I2C-bus acknowledge output

SDA[1]

4 to 6

I2C-bus serial data input

SCL

7 to 9

I2C-bus serial clock input

CLK

clock input and output

VDD

11 to 13

supply voltage

SYNC

cascade synchronization input and output

OSC

selection of internal or external clock

T1, T2 and T3

16, 17 and 18 to 20

dedicated testing pins; to be tied to VSS in

application mode

A0 and A1

21, 22

subaddress inputs

SA0

I2C-bus slave address input

VSS[2]

24 to 26

ground supply voltage

VLCD

27 to 29

LCD supply voltage

BP2 and BP0

30, 31

LCD backplane outputs

S0 to S79

32 to 111

LCD segment outputs

BP0, BP2, BP1, and BP3

112 to 115

LCD backplane outputs

S80 to S159

116 to 195

LCD segment outputs

BP3 and BP1

196, 197

LCD backplane outputs

PCA85232DA bảng dữ liệu(PDF) 5 Page - NXP Semiconductors

PCA85232DA bảng dữ liệu(HTML) 5 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

bảng dữ liệu tải về

Link URL