P89LPC922A1FDH datasheet(30/75 Pages) NXP

tên linh kiện	P89LPC922A1FDH

Giải thích chi tiết về linh kiện	8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC

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P89LPC92X1

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Product data sheet

Rev. 2 — 1 December 2010

30 of 75

NXP Semiconductors

P89LPC9201/9211/922A1/9241/

8-bit microcontroller with 8-bit ADC

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

7.15.1 External interrupt inputs

The P89LPC9201/9211/922A1/9241/9251 has two external interrupt inputs as well as the

Keypad Interrupt function. The two interrupt inputs are identical to those present on the

standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC9201/9211/922A1/9241/9251 is put

into Power-down or Idle mode, the interrupt will cause the processor to wake-up and

resume operation. Refer to Section 7.18 “Power reduction modes” for details.

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